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| AME, Inc. AT209S n General Description The AT209S is an integrated device that contains a PCI Arbiter and a Clock Buffer. PCI Arbiter extends system PCI devices without piecing other circuit to simplify design complexity and increase systems stability. PCI Arbiter also provides STOP# input pin with that extended PCI devices instruct the master to prematurely end the transaction on the current data phase same as one in PCI specification. Clock Buffer is a high performance and low jitter zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKO feed back to the input of a build-in PLL. PCICLKI is the clock input of the Clock Buffer. In the absence of PCICLKI input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. PCI Arbiter and Clock Buffer n Features l PCI Arbiter Extend PCI Devices from One to Three l PCI Clock Frequency Support PCI Clock range from 25MHz to 66MHz l Zero delay buffer Generate four zero delay clock sources Support frequency range from 25MHz to 66MHz l All AME's Lead Free Products Meet RoHS Standards Rev.A.01 1 AME, Inc. AT209S n Pin Configuration PCI Arbiter and Clock Buffer NC P C IS T O P # S YS R E Q # S YS G N T # P C IR E Q 1 # VSS P C IG N T 1 # P C IR E Q 2 # VCC P C IG N T 2 # P C IR E Q 3 # P C IG N T 3 # NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 AVCC P C IC L K I P C IR S T # AVSS VSS P C IC L K O U T P C IC L K 1 VCC P C IC L K 2 P C IC L K 3 P C IC L K 4 VSS NC NC A T 2 0 9 S 24 23 22 21 20 19 18 17 16 15 Ordering Information AT209S- Commercial Standard AT209SG- Green Device with Commercial Standard 2 Rev.A.01 AME, Inc. AT209S n Pin Description I/O Type IN OUT PWR PCI Arbiter and Clock Buffer Function Input Pin Output Pin Power Pin Pin No. 26 2 3 4 5 7 8 10 11 12 Pin Name PCIRST# PCISTOP# SYSREQ# SYSGNT# PCIREQ1# PCIGNT1# PCIREQ2# PCIGNT2# PCIREQ3# PCIGNT3# I/O Type IN IN OUT IN IN OUT IN OUT IN OUT PCI bus reset# Function PCI bus stop# (Internal 47K pull-up resistor) Request signal to chipset Grant signal from chipset (Internal 47K pull-up resistor) Request signal from PCI bus (Internal 47K pull-up resistor) Grant signal to PCI bus Request signal from PCI bus (Internal 47K pull-up resistor) Grant signal to PCI bus Request signal from PCI bus (Internal 47K pull-up resistor) Grant signal to PCI bus Table 1. PCI Arbiter FSM Group Signal, Power; Vcc3V (3.3V) Rev.A.01 3 AME, Inc. AT209S n Pin Description Pin No. 18 19 20 22 23 27 PCI Arbiter and Clock Buffer Pin Name PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLKOUT PCICLKI I/O Type OUT OUT OUT OUT OUT IN PCICLK output PCICLK output PCICLK output PCICLK output Function PLL feedback and Internal feedback on this pin PCLCLK input reference frequency Table 2. Clock Buffer Group Signal ---- Power: Vcc23 (2.5V or 3.3V) Pin No. 6 9 17 21 24 25 28 Pin Name VSS VCC VSS VCC VSS AVSS AVCC I/O Type PWR PWR PWR PWR PWR PWR PWR Ground 3.3V Power Ground 3.3V Power Ground Ground for PLL 3.3V Power for PLL Function Table 3. Power Signal 4 Rev.A.01 AME, Inc. AT209S n Quick Reference Data GND = 0V; VCC = 3.3V; 0oC < Temp < 85oC PCI Arbiter and Clock Buffer Symbol VCC VSS AVCC AVSS Parameter Power pin Ground pin Power pin for PLL Ground pin for PLL Test Conditions Min 3.15 Typical 3.3 0 Max 3.45 Unit V V 3.15 3.3 0 3.45 V V Table 4. Power/Ground Pin Symbol Vil Vih Vol Voh Duty1 Parameter Input low voltage Input high voltage Output low voltage Output high voltage Output duty cycle (0.5*VCC as a reference) Output rise time Test Conditions Min 2 Typical Max 0.8 Unit V V IoI=30mA; VCC3V=3.3V Ioh=30mA; VCC3V=3.3V Input duty cycle=50% Measure between 0.8v and 2V, 2.4 45 0.4 V V 55 % Tr 2 CL=30P Measure between 0.8v and 2V, CL=30P Measure at 0.5*Vin & Vout, nS Tf Output fall time 2 nS Tpd PCICLKI Propagation delay time Buffer input frequency CL=30P 25M 250 50M nS Hz Table 5. Clock Buffer Block Rev.A.01 5 AME, Inc. AT209S n Quick Reference Data Symbol Vil Vih Vol Voh Tdcko PCI Arbiter and Clock Buffer Parameter Input low voltage Input high voltage Output low voltage Output high voltage Output delay from PCICLK rising edge to output valid Test Conditions Min 2.0 Typical Max 0.8 Unit V V 0.4 2.4 8 10 V nS nS Table 6. PCI Arbiter FSM 6 Rev.A.01 AME, Inc. AT209S PCI Arbiter and Clock Buffer PLL PCICLKI PCICLKOUT PCICLK1 PCICLK2 PCICLK3 PCICLK4 Figure 2. Clock Buffer Block Diagram Output-to-Output Skew Since the PCICLKOUT and the PCICLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. If all outputs are equally loaded, zero phase difference will maintained from PCICLKI to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the PCICLK(1-4) outputs are less loaded than PCICLKOUT, PCICLK(1-4) outputs will lead it; and if the PCICLK(1-4) is more loaded than PCICLKOUT, PCICLK(1-4) will lag the PCICLKOUT. Rev.A.01 7 AME, Inc. AT209S PCI Arbiter and Clock Buffer Zero Delay PCICLKI input and all outputs loaded Equally PCICLKI PCICLKOUT PCICLK(1-4) PCICLKI PCICLKOUT PCICLKI PCICLKOUT PCICLK(1-4) Advanced PCICLK(1-4) Delayed PCICLKI input and PCICLK(1-4) outputs loaded equally, with PCICLKOUT loaded More. PCICLKI input and PCICLK(1-4) outputs loaded equally, with PCICLKOUT loaded Less. Figure 3. Timing diagrams with different loading configurations 8 Rev.A.01 AME, Inc. AT209S n Package Dimension SSOP-28 MILLIMETERS MIN 1.35 0.10 0.20 9.80 3.81 5.80 0.41 0o MAX 1.75 0.25 1.50 0.30 10.00 4.00 6.20 1.27 8o INCHES MIN 0.053 0.004 0.008 0.386 0.150 0.228 0.016 0o MAX 0.069 0.010 0.059 0.012 0.394 0.157 0.244 0.500 8o PCI Arbiter and Clock Buffer TOP VIEW 28 15 SYMBOLS A A1 A2 E E1 b D E1 e E h L 1 b e 14 0.635BASIC 0.380BASIC 0.025BASIC 0.015BASIC FRONT VIEW D A2 A1 A SEATING PLANE 0.004 max SIDE VIEW Rev.A.01 h A" GAUGE PLANE 0' L SEATING PLANE DETAL : A" 9 www.ame.com.tw E-Mail: sales@ame.com.tw Life Support Policy: These products of AME, Inc. are not authorized for use as critical components in life-support devices or systems, without the express written approval of the president of AME, Inc. AME, Inc. reserves the right to make changes in the circuitry and specifications of its devices and advises its customers to obtain the latest version of relevant information. (c) AME, Inc. , Auguest 2007 Document: ATT-DS209S-A.01 Corporate Headquarter AME, Inc. 2F, 302 Rui-Guang Road, Nei-Hu District Taipei 114, Taiwan. Tel : 886 2 2627-8687 Fax: 886 2 2659-2989 U.S.A. (Subsidiary) Analog Microelectronics, Inc. 3100 De La Cruz Blvd., Suite 201 Santa Clara, CA. 95054-2046 Tel: (408) 988-2388 Fax: (408) 988-2489 |
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